Reference current generator for resistance type memory and method thereof

ABSTRACT

A reference current generator for a resistance type memory and a method thereof is disclosed. The reference current generator comprises N parallel circuit sets. Each of the N parallel circuit sets is formed with at least one first reference element and second reference elements connected in parallel. The number of the first reference elements plus the number of the second reference elements is N. The resistance value of first reference elements (a first resistance value) is not equal to the resistance value of the second reference elements (a second resistance value). An equivalent resistance provided with a equivalent resistance value between the first and second resistance value is formed by connecting the N parallel circuit sets in series between an input terminal and output terminal. A reference current is outputted from the output terminal by applying an operation voltage to the input terminal.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a reference current generator for aresistance type memory and a method thereof, and more particularly to agenerator capable of generating an accurate and reliable referencecurrent and a method thereof.

(b) Description of the Prior Art

Currently, a typical memory is comprised of a plurality of memory cells.Each memory cell is utilized to store 1-bit data, and the data state maybe written to or read out from the cell. Different resistance values ofthe memory cell correspond to different logic states of the stored data.In a non-volatile memory, it is necessary to provide a current source ora voltage source to a selected memory cell during reading of data fromthe memory. The logic states of data stored in the memory cell isdetermined by the output sense current. However, due to thenon-uniformity of semiconductor manufacturing process, thecharacteristics of memory cells in memory are different from each otherso that their resistance values are changed and the sense current valuesare also shifted, which leads to incorrect interpretation. Therefore,the logic states of data stored in a memory cell are often determined bythe comparison of the sense currents with reference currents generatedby a reference current generator.

Referring to FIG. 1, a schematic view showing sense currentdistributions of two logic states of a stored datum is illustrated. Inthis figure, the abscissa represents the magnitude of the sense currentand the ordinate represents the number of memory cells corresponding tothe sense currents correspond. Generally, the distribution of memorycells is a Gaussian distribution as shown in the figure. When theresistance value of a memory cell is Rmax, the logic state of thecorresponding data is 0 and the sense current is I₀. When the resistancevalue of a memory cell is Rmin, the logic state of the correspondingdata is 1 and the sense current is I₁. Iref represents a referencecurrent. When the resistance value of a memory cell varies, thecorresponding sense current also varies within a certain range.Therefore, it is necessary to determine the logic state of read data bythe comparison of the sense current with a reference current. When thesense current is less than Iref, the resistance value of the memory cellis around Rmax. As a result, the logic state is determined as 0. Whenthe sense current is greater than Iref, the resistance value of thememory cell is around Rmin As a result, the logic state is determined as1.

Referring to both FIGS. 2A and 2B, there are illustrated a graphicalrepresentation illustrating the relationship of various resistancesdiscussed and a schematic view showing a midpoint resistance generatoraccording to the prior art of U.S. Pat. No. 6,392,923. In a memory cell,an element with a maximum resistance value (Rmax) is connected in serieswith an element with a minimum resistance value (Rmin) to form a seriescircuit. Then, two series circuits are connected in parallel to obtainan equivalent midpoint resistance (Rmid) with a resistance value of(Rmax+Rmin)/2. The current passing through the generator is not amidpoint current. Thus it is unsuitable for the operation for utilizingthe output current value as a reference for determining the logic state,but is only suitable for the operation for utilizing the output voltagevalue as a reference for determining the logic state.

In another prior art patent, U.S. Pat. No. 7,286,395 discloses twomemory cells with different resistance characteristics (Rmax, Rmin) areconnected in parallel to obtain an equivalent resistance Rmax//Rmin Thegenerator becomes a midpoint current generator by averaging the outputcurrents passing through the generator. However, the generator has apoor resistance capability against resistance variations caused bysemiconductor manufacturing process.

SUMMARY OF THE INVENTION

In view of the aforementioned problems of the prior art, one object ofthe present invention is to provide a reference current generator for aresistance type memory for generating a reference current signalcompared with the sense current passing through a non-volatile memorythereby avoiding incorrect determination caused by the differencebetween of each memory cell of the non-volatile memory due tosemiconductor manufacturing process.

According to another object of the present invention reference currentgenerator for a resistance type memory is provided, comprising Nparallel circuit sets, where N is an integer greater than 1, each of theN parallel circuit sets is formed with at least one first referenceelement and at least one second reference element in parallel to eachother. The number of the first reference elements plus the number of thesecond reference elements is N in each parallel circuit set. Each firstreference element has a first resistance value and each second referenceelement has a second resistance value different from the firstresistance value. N parallel circuit sets are connected in seriesbetween an input terminal and an output terminal to form an equivalentresistance whose resistance value is between the first resistance valueand the second resistance value. A reference current is outputted fromthe output terminal by applying an operation voltage to the inputterminal. The N parallel circuit sets are connected in series betweenthe input terminal and the output terminal so that the inherentvariation of characteristics among the reference elements in thegenerator is corrected to provide a more accurate reference current.

Wherein, the first reference element and the second reference elementeach is formed with a non-volatile resistance element and a switchingtransistor connected in series.

Wherein, the generator further comprises N control terminals, and eachcontrol terminals is respectively connected to a gate of the switchingtransistor of each first reference elements and each second referenceelements in each parallel circuit sets to provide N bias voltagescorrespondingly.

When the number of the first reference elements is equal to the numberof the second reference elements, the resistance value of the resultedequivalent resistance is between the first resistance value and thesecond resistance value. The value of current passing through theequivalent resistance is a midpoint between the current values sensed bythe first reference element and the second reference element.

Furthermore, the present invention provides a method for generating areference current for a resistance type memory comprising the followingsteps. First, a parallel circuit set is provided by connecting at leastone first reference element whose resistance value is a first resistancevalue and at least one second reference element whose resistance valueis a second resistance value in parallel with each other, wherein thefirst resistance value is not equal to the second resistance value. Theabove procedure is repeated to form parallel circuit sets. The number ofthe first reference elements plus the number of the second referenceelements is N in each parallel circuit. An equivalent resistance havinga equivalent resistance value between the first resistance value and thesecond resistance value is provided by connecting the N parallel circuitsets in series between an input terminal and an output terminal.Finally, a reference current is outputted from the output terminal byapplying an operation voltage to the input terminal.

As described above, the reference current generator for a resistancetype memory and the method thereof according to the present inventionmay have the following advantages:

(1) The reference current generator may generate a reference currentsignal compared with the sense current passing through a non-volatilememory thereby avoiding incorrect determination caused by the differencebetween of each memory cell of the non-volatile memory due tosemiconductor manufacturing process.

(2) The reference current generator may correct the inherent variationof characteristics among the reference elements in the generator by theseries connection of N parallel circuit sets to provide a more accuratereference current.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic view showing sense current distributions of twologic states of a stored datum according to the present invention;

FIG. 2A is a graphical representation illustrating the relationship ofvarious resistances discussed;

FIG. 2B is a schematic view showing a midpoint resistance generatoraccording to the prior art;

FIG. 3 is a schematic view of a first embodiment of a reference currentgenerator for a resistance type memory according to the presentinvention;

FIG. 4A is a schematic view showing a first reference element underforward bias voltage according to the present invention;

FIG. 4B is a schematic view showing a second reference element underforward bias voltage element according to the present invention;

FIG. 4C is a schematic view showing a first reference element underreversed bias voltage according to the present invention;

FIG. 4D is a schematic view showing a second reference element underreversed bias voltage according to the present invention;

FIG. 5 is a schematic view of a second embodiment of a reference currentgenerator for a resistance type memory according to the presentinvention;

FIG. 6 is a schematic view of a third embodiment of a reference currentgenerator for a resistance type memory according to the presentinvention;

FIG. 7 is a schematic view of a fourth embodiment of a reference currentgenerator for a resistance type memory according to the presentinvention;

FIG. 8 is a schematic view of a fifth embodiment of a reference currentgenerator for a resistance type memory according to the presentinvention; and

FIG. 9 is a flow chart of the implementation steps of a method forgenerating a reference current for a resistance type memory according tothe present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention discloses a reference current generator for aresistance type memory, comprising N parallel circuit sets, where N isan integer greater than 1, are connected in series between an inputterminal and an output terminal to provide an equivalent resistance.Then, a reference current is outputted from the output terminal byapplying an operation voltage to the input terminal.

Each parallel circuit sets is formed with at least one first referenceelement whose resistance value is a first resistance value and at leastone second reference element whose resistance value is a secondresistance value connected in parallel with each other. The number ofthe first reference elements plus the number of the second referenceelements is N in each parallel circuit.

Wherein, the equivalent resistance value is between the first resistancevalue and the second resistance value.

Referring to FIG. 3, a schematic view of a first embodiment of areference current generator for a resistance type memory according tothe present invention is illustrated. In this figure, the referencecurrent generator for a resistance type memory comprises two parallelcircuit sets (31), an input terminal (32), an output terminal (33), andtwo control terminals (34). Each of the two parallel circuit sets (31)is formed with a first reference element (311) and a second referenceelement (312) connected in parallel with each other. The resistancevalue of each first reference elements (311) is a first resistance value(R1), and the resistance value of each second reference elements (312)is a second resistance value (R2), and wherein R1 is greater than R2. Anequivalent resistance (Re) is provided by connecting the two parallelcircuit sets (31) in series between the input terminal (32) and theoutput terminal (33), and Re is between R1 and R2. Then, a reference isoutputted from the output terminal (33) by applying an operation voltageto the input terminal (32). Also referring to FIGS. 4A, 4B, 4C and 4D,there are illustrated a schematic view showing a first reference elementunder forward bias voltage, a schematic view showing a second referenceelement under forward bias voltage, a schematic view showing a firstreference element under reversed bias voltage, and a schematic viewshowing a second reference element under reversed bias voltage. In thesefigures, each of the first reference element (311) and the secondreference element (312) are formed with a variable resistance element(3101) and a switching transistor (3102) connected in series. Each twocontrol terminals (34) is connected to the gate (3103) of each switchingtransistor in each of the parallel circuit sets (31), so as to providethe bias voltages required by the two parallel circuit sets. The biasvoltage values may be the same or different from each other. When thevariable resistance element (3101) is connected in series to theswitching transistor (3102) as illustrated in FIGS. 4A and 4B, a forwardbias voltage is provided by each of the control terminals (34). When theswitching transistor (3102) is connected in series to the variableresistance element (3101) as illustrated in FIGS. 4C and 4D, a reversedbias voltage is provided by each of the control terminals (34).

When an operation voltage is applied to the first reference element(311), a current I₁ is generated. When an operation voltage is appliedto the second reference element (312), a current 1 ₂ is generated. Thegenerated reference current in the first embodiment is a midpointcurrent having a current value of (1 ₁+I₂)/2. This reference current maybe used to compare with a sense current. If the sense current is greaterthan the reference current, it means that a logic state of stored datain a memory cell corresponds to a state at a smaller resistance value.If the sense current is less than the reference current, it means that alogic state of stored data in a memory cell corresponds to a state at alarger resistance value.

If the resistance values of the first reference element and the secondreference element are 5 KΩ and 8 KΩ respectively as well as theoperation voltage is 0.3 V, the currents passing through the firstreference element (311) and the second reference element (312) are 37.5μA (I₁) and 60 μA (I₂) respectively. The ideal midpoint current value is48.75 μA. In the prior art of U.S. Pat. No. 6,392,923, the generatedequivalent resistance is about 6.5 KΩ, and the reference current valueis 46.15 μA different from the ideal midpoint current value. Thegenerated equivalent resistance in the first embodiment is about 6.15KΩ, and the reference current value is 48.75 μA as same as the idealmidpoint current value. Further, it is assumed that the resistancevariation between the reference elements is 1 KΩ, i.e. the resistancevalue of the first reference element (311) ranging from 4 to 6 KΩ andthe resistance value of the second reference element (312) ranging from7 to 9 KΩ. Compared to the prior art of U.S. Pat. No. 7,286,395, thegenerated equivalent resistance is between 2.55 and 3.6 KΩ, and thereference current value is 118 to 83 μA. The value of the referencecurrent generated by this method is I₁+I₂. If it is desired to comparewith I₁ or 1 ₂, the value of the reference current must be reduced to ahalf, (I₁+I₂)/2. So, the reference current value is 59 to 41.5 μA. Thegenerated equivalent resistance in the first embodiment is between 5.58and 6.68 KΩ, and the reference current value is between 44.9 and 53.7μA. Therefore, the generated reference current in the first embodimenthas a more dense distribution than the reference current generated inthe prior art under a condition of the same resistance variation.Namely, the reference current generator for a resistance type memoryaccording to the present invention has a better resistance capabilityagainst resistance variations to provide an exact read and determinationfunction to a memory.

Referring to FIG. 5, a schematic view of a second embodiment of areference current generator for a resistance type memory according tothe present invention is illustrated. Compared to the first embodiment,the difference lies in that there are three parallel circuit sets (51).Each of parallel circuit sets (51) is formed with two first referenceelements (511) and a second reference element (512) connected inparallel with each other. Three control terminals (54) are respectivelyconnected to the gates of switching transistors in the parallel circuitsets (51), so as to provide the bias voltages required by the respectivethree parallel circuit sets (51).

When an operation voltage is applied to the first reference element(511), a current I₁ is generated. When an operation voltage is appliedto the second reference element (512), a current I₂ is generated. Thegenerated reference current in this embodiment has a current value of(2I₁+I₂)/3. If each of the parallel circuit sets (51) is formed with afirst reference element (511) and two second reference elements (512)connected in parallel with each other, the generated reference currentvalue is (I₁+2I₂)/3. According to these two different reference currentvalues, the adjustment of a sensing margin may be optimized or threedifferent logic states of data may be interpreted.

Referring to FIG. 6, a schematic view of a third embodiment of areference current generator for a resistance type memory according tothe present invention is illustrated. Compared to the first embodiment,the difference lies in that there are four parallel circuit sets (61).Each parallel sets (61) is formed with two first reference elements(611) and two second reference elements (612) connected in parallel witheach other. Four control terminals (64) are respectively connected tothe gates of switching transistors in the parallel circuit sets (61), soas to provide the bias voltages required by the respective four parallelcircuit sets (61).

The generated reference current in the third embodiment is the same asthat in the first embodiment. The reference current is a midpointcurrent having a current value of (I₁+I₂)/2. But there is a more densedistribution of the generated reference currents in the third embodimentso that the generator has a better resistance capability againstresistance variations to allow a memory to perform exact reading anddetermination.

Referring to FIG. 7, a schematic view of a fourth embodiment of areference current generator for a resistance type memory according tothe present invention is illustrated. Compared to the third embodiment,the difference lies in that each of the parallel circuit sets (71) isformed with three first reference elements (711) and a second referenceelements (712) connected in parallel with each other. The resultedequivalent resistance value is also different from the equivalentresistance value in the third embodiment.

The generated reference current in the fourth embodiment has a currentvalue of (3I₁+I₂)/4. But if each the parallel circuit sets (71) isformed with a first reference element (711) and three second referenceelements (712) connected in parallel with each other, as well as twofirst reference elements (711) and two second reference elements (712)connected in parallel with each other, the generated reference currentvalues are (I₁+3I₂)/4 and (2I₁+2I₂)/4, in sequence. According to thethree different reference current values, the adjustment of a sensingmargin may be optimized or four different logic states of data may beinterpreted.

Referring to FIG. 8, a schematic view of a fifth embodiment of areference current generator for a resistance type memory according tothe present invention is illustrated. Compared to the first embodiment,the difference lies in that there are N parallel circuit sets (81), eachof which is formed with a first reference element (811) and (N−1) secondreference elements (812) connected in parallel with each other. Ncontrol terminals (84) are respectively connected to the gates ofswitching transistors in the parallel circuit sets (81), so as toprovide the bias voltages required by the respective N parallel circuitsets (81).

The generated reference current in the fifth embodiment has a currentvalue of (I₁+(N−1)I₂)/N. If, in each parallel circuit sets (81), thenumber of first reference elements (811) increases, in turn, the numberof second reference elements (812) decreases, the generated referencecurrent values are (2I₁+(N−2)I₂)/N, (3I₁+(N−3)I₂)/N, . . . , and((N−1)I₁+I₂)/N, in sequence. According to these N−1 different referencecurrent values, N different logic states of data may be interpreted.

Referring to FIG. 9, illustrated is a flow chart of the implementationsteps of a method for generating a reference current for a resistancetype memory according to the present invention. In this figure, thegeneration method comprises the following steps. In step S1, providing aparallel circuit set by connecting at least one first reference elementand at least one second reference element in parallel to each other. Instep S2, the same procedure is used to form N parallel circuit sets. Instep S3, providing an equivalent resistance by connecting the N parallelcircuit sets in series between an input terminal and an output terminalto provide an equivalent resistance. In step S4, outputting a referencecurrent from the output terminal by applying an operation voltage to theinput terminal.

In each parallel circuit sets, the number of the first referenceelements plus the number of the second reference elements is N.

The resistance value of each of the first reference elements is a firstresistance value. The resistance value of each of the second referenceelements is a second resistance value different from the firstresistance value.

The equivalent resistance value is between the first resistance valueand the second resistance value.

Referring to FIG. 3, the first embodiment of the present invention istaken as an example. A first reference element (311) and a secondreference element (312) are connected in parallel with each other toprovide a parallel circuit set (31). The same procedure is used to formanother parallel circuit set (31). These two parallel circuit set (31)are connected in series between an input terminal (32) and an outputterminal (33) to provide an equivalent resistance. An operation voltageis applied to the input terminal (32) so that the output terminal (33)outputs a reference current.

The resistance value of each of the first reference elements is a firstresistance value. The resistance value of each of the second referenceelements is a second resistance value. The first resistance value is notequal to the second resistance value.

The equivalent resistance value is between the first resistance valueand the second resistance value.

The above description is illustrative only and is not to be consideredlimiting. Various modifications or changes can be made without departingfrom the spirit and scope of the invention. All such equivalentmodifications and changes shall be included within the scope of theappended claims.

1. A reference current generator for a resistance type memory,comprising: N parallel circuit sets, where N is an integer greater than1, each of the N parallel circuit sets being formed with at least onefirst reference element and at least one second reference elementconnected in parallel to each other, and the number of the firstreference elements plus the number of the second reference elementsbeing N in each of the N parallel circuit sets, and each of the firstreference elements being provided with a first resistance value and eachof the second reference elements being provided with a second resistancevalue different from the first resistance value; and N controlterminals, each of the N control terminals respectively connected to agate of a switching transistor of each of the first reference elementsand each of the second reference elements in each of the N parallelcircuit sets to provide N bias voltages correspondingly; wherein the Nparallel circuit sets are connected in series between an input terminaland an output terminal to form an equivalent resistance provided with aequivalent resistance value between the first resistance value and thesecond resistance value, and a reference current is outputted from theoutput terminal by applying an operation voltage to the input terminal;wherein each of the first reference elements is formed with anon-volatile resistance element and the switching transistor connectedin series to the non-volatile resistance element, and each of the secondreference elements is formed with the non-volatile resistance elementand the switching transistor connected in series to the non-volatileresistance element.
 2. The reference current generator for a resistancetype memory of claim 1, wherein voltage values of each of the N biasvoltages are the same.
 3. The reference current generator for aresistance type memory of claim 1, wherein voltage values of each of thebias voltages are different from each other.
 4. The reference currentgenerator for a resistance type memory of claim 1, wherein a firstreference current is generated by applying the operation voltage to thefirst reference element; a second reference current is generated byapplying the operation voltage to the second reference element, and whenthe number of the first reference elements is equal to the number of thesecond reference elements, the reference current is a midpoint current,that is, the reference current is a half of the sum of the firstreference current and the second reference current.
 5. A method forgenerating a reference current for a resistance type memory, comprisingthe following steps: providing a parallel circuit set by connecting atleast one first reference element and at least one second referenceelement in parallel to each other; repeating the above procedure to formN parallel circuit sets; forming an equivalent resistance by connectingthe N parallel circuit sets in series between an input terminal and anoutput terminal; outputting a reference current from the output terminalby applying an operation voltage to the input terminal; and providing Ncontrol terminals, each of the N control terminals respectivelyconnected to a gate of a switching transistor of each of the firstreference elements and the each of the second reference elements in eachof the N parallel circuit sets to provide N bias voltagescorrespondingly; wherein the number of the first reference elements plusthe number of the second reference elements is N in each of the Nparallel circuit sets; wherein each of the first reference elements isprovided with a first resistance value and each of the second referenceelements is provided with a second resistance value different from thesecond resistance value; wherein a equivalent resistance value isbetween the first resistance value and the second resistance value;wherein each of the first reference elements is formed with anon-volatile resistance element and the switching transistor connectedin series to the non-volatile element, and each of the second referenceelements is formed with the non-volatile resistance element and theswitching transistor connected in series to the non-volatile resistanceelement.
 6. The method for generating a reference current for aresistance type memory of claim 5, wherein voltage values of each of theN bias voltages are the same.
 7. The method for generating a referencecurrent for a resistance type memory of claim 5, wherein voltage valuesof each of the bias voltages are different from each other.
 8. Themethod for generating a reference current for a resistance type memoryof in claim 5, wherein a first reference current is generated byapplying the operation voltage to the first reference element; a secondreference current is generated by applying the operation voltage to thesecond reference element, and when the number of the first referenceelements is equal to the number of the second reference elements, thereference current is a midpoint current, that is, the reference currentis a half of the sum of the first reference current and the secondreference current.